1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a driving method thereof to prevent deterioration of picture quality.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal having a dielectric anisotropy using an electric field thereby displaying a picture. To this end, the LCD includes a liquid crystal display panel for displaying a picture and a driving circuit for driving the liquid crystal display panel. In the liquid crystal display panel, liquid crystal cells control light transmittance in accordance with pixel signals to thereby display a picture. The driving circuit includes a gate driver for driving gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling a driving timing of the gate driver and the data driver, and a power supply for supplying power signals required for driving the liquid crystal display panel and the driving circuit.
The data driver and the gate driver are separated into a plurality of integrated circuits (IC's) that are manufactured as chips. Each of the integrated drive IC's is mounted in an open IC area of a tape carrier package (TCP) or in a base film of the TCP by a chip on film (COF) system, and is electrically connected to the liquid crystal display panel by tape automated bonding (TAB) system. Alternatively, the drive IC may be directly mounted onto the liquid crystal display panel by a chip on glass (COG) system. The timing controller and the power supply are manufactured as a chip and mounted on a main printed circuit board (PCB).
The drives IC's connected to the liquid crystal display panel by the TCP are connected, via a flexible printed circuit (FPC) and a sub-PCB, to the timing controller and the power supply on the main PCB. More specifically, the data drive IC's receive data control signals and pixel data from the timing controller mounted onto the main PCB and power signals from the power supply by way of the FPC and the data PCB. The gate drive IC's receive gate control signals from the timing controller mounted onto the main PCB and power signal from the power supply by way of the PCB.
The drive IC's mounted onto the liquid crystal display panel by the COG system receive control signals from the timing controller mounted onto the main PCB and power signals from the power supply through the FPC and line on glass (LOG) type signal lines provided at the liquid crystal display panel. Even when the drive IC's are connected, via the TCP, to the liquid crystal display panel, the LCD adopts the LOG-type signal lines to eliminate the PCB, thereby having a thinner thickness. Particularly, the gate PCB delivering a relatively small number of signals is removed, and signal lines for applying gate control signals and power signals to the gate drive IC's are provided on the liquid crystal display panel in a LOG type. Thus, the gate drive IC's mounted in the TCP receives the control signals from the timing controller and the power signals from the power supply by way of the main PCB, FPC, the data PCB, the data TCP, the LOG-type signal lines and the gate TCP in turn. In this case, the gate control signals and the gate power signals applied to the gate drive IC's are distorted by line resistances of the LOG-type signal lines, thereby causing quality deterioration in a picture displayed on the liquid crystal display panel.
FIG. 1 is a schematic plan view showing a configuration of a related art line on glass (LOG) type liquid crystal display. As shown in FIG. 1, a LOG-type LCD having no gate PCB includes a main PCB 20 having a timing controller 22 and a power supply 24, a data PCB 16 connected, via a FPC 18, to the main PCB 20, a data TCP 12 having a data driving IC 14 connected between the data PCB 16 and liquid crystal display panel 6, and a gate TCP 8 having with a gate driving IC 10 connected to the liquid crystal display panel 6.
In the liquid crystal display panel 6, a thin film transistor array substrate 2 and a color filter array substrate 4 are joined to each other and have a liquid crystal therebetween. Such a liquid crystal display panel 6 is provided with liquid crystal cells driven independently by respective thin film transistors, which are adjacent to where gate lines GL and data lines DL cross each other. More particularly, the thin film transistor applies a pixel signal from the data line DL to the liquid crystal cell in response to a scanning signal from the gate line GL.
The data drive IC 14 is connected, via the data TCP 12 and a data pad of the liquid crystal display panel, to the data line DL. The data drive IC 14 converts a pixel data into an analog pixel signal and applies it to the data line DL. The data drive IC 14 receives a data control signal, a pixel data and power signals from the timing controller 22 and the power supply 24 mounted onto the main PCB 20 by way of the data PCB 16 and the FPC 18.
The gate drive IC 10 is connected, via the gate TCP 8 and a gate pad of the liquid crystal display panel 6, to the gate line GL. The gate drive IC 10 sequentially applies a scanning signal having a gate high voltage VGH to the gate lines GL. Further, the gate drive IC 10 applies a gate low voltage VGL to the gate lines GL in the remaining interval excluding a time interval when the gate high voltage VGH has been supplied.
The gate control signals and the power signals from the timing controller 22 and the power supply 24 on the main PCB 20 are applied, via the FPC 18 and the data PCB 16, to the data TCP 12. The gate control signals and the power signals applied via the data TCP 12 are applied, via a LOG-type signal line group 26 provided at the edge area of the thin film transistor array substrate 2, to the gate TCP 8. The gate control signals and the power signals applied to the gate TCP 8 are input via input terminals of the gate drive IC 10. Further, the gate control signals and the power signals are outputted via output terminals of the gate drive IC 10, and applied, via the gate TCP 8 and the LOG-type signal line 26, to the gate drive IC 10 mounted in the next gate TCP 8.
The LOG-type signal line group 26 includes signal lines for supplying direct current driving voltages from the power supply 24, such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND and a base driving voltage VCC; and gate control signals from the timing controller 22, such as a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE. Such a LOG-type signal line group 26 is formed from the same gate metal layer as the gate lines at a specific pad area of the thin film transistor array substrate 2 in a fine pattern. Further, the LOG-type signal line group 26 is in contact with the gate TCP 8 at contact portion A, which has a contact resistance. Thus, the LOG-type signal line group 26 has a larger line resistance than signal lines on a gate PCB. This line resistance distorts gate control signals (i.e., GSP, GSC and GOE) and power signals (i.e., VGH, VGL, VCC, GND and VCOM) transmitted via the LOG-type signal line group 26, thereby generating a horizontal stripe and/or stain, which causes a deterioration of picture quality, such as cross talk in a dot pattern and a greenish hue.
FIG. 2 is a view for explaining a horizontal line stripe phenomenon in the liquid crystal display panel shown in FIG. 1. As shown in FIG. 2, the LOG-type signal line group 26 supplying the gate control signals (i.e., GSP, GSC and GOE) and power signals (VGH, VGL, VCC, GND and VCOM) is comprised of first to third LOG-type signal line groups LOG1 to LOG3 between the gate TCPs 8. The first to third LOG-type signal line groups LOG1 to LOG3 have line resistances aΩ, bΩ and cΩ proportional to the line length thereof, respectively, and are connected, via the gate TCP 8 and the gate drive IC 10, to each other in series. The first to third LOG-type signal line groups LOG1 to LOG3 generate a level difference between the gate control signals (i.e., GSP, GSC and GOE) and power signals (VGH, VGL, VCC, GND and VCOM) input for each gate drive IC 10. As a result, a brightness difference is generated between horizontal line blocks A to C that are driven by different gate drive IC's and thereby cause the appearance of a horizontal line stripe 32.
The first gate drive IC 10 is supplied with gate control signals GSP, GSC and GOE and power signals VGH, VGL, VCC, GND and VCOM across a line resistance aΩ of the first LOG-type signal line group LOG1; the second gate drive IC 10 is supplied with such gate control signals across line resistances aΩ+bΩ of the first LOG-type signal line group LOG1 and the second LOG-type signal line group LOG2; and the third gate drive IC 10 is supplied with gate control signals across line resistances aΩ+bΩ+cΩ of the first to third LOG-type signal line groups LOG1 to LOG3. Thus, a different voltage drop is generated among scanning pulses VG1 to VG3 applied to the gate lines at the first to third horizontal blocks A to C driven by different gate drive IC's 10, thereby causing horizontal line stripes 32 among the horizontal line blocks A to C.